| Job Location | Bayan, Malaysia |
| Education | Not Mentioned |
| Salary | Not Mentioned |
| Industry | Other |
| Functional Area | Not Mentioned |
ASIC Physical Design EngineerResponsibilities include (but not limited to): You will be participating in the leading-edge System-On-a-Chip (SoC) design projects usingcutting-edge process technology nodes for various client applications. Ideate, develop, and execute physical design solutions. Participate in design/architecture reviews. Evaluate and deploy the evolving physical design methodologies to handle increasingly complexSoC/IP designs within aggressive, market-driven schedules. Active participation in benchmarking of library, technology parameters, and implementationstrategy to enable design requirements of die size, power & speed. Enable technological innovations from day-to-day learning and project experiences. Actively work as part of a team both locally and also with remote or multi-site teams. Macroblock and chip level floor planning of digital logic, memories, IOs. Full chip timing constraints development, full chip Static Timing Analysis, and Signoff for acomplex, multi-clock, multi-voltage SoC. Analyze and incorporate advance timing signoff flows (SSTA, LOCV Based STA, IR Drop awareSTA) into SoC timing signoff flow. Active participation to enhance the flow from the front end (pre-layout) to the back end (post-layout) at both chip level and block level.Minimum Qualifications: Minimum of a Bachelors degree in Electrical and/or Electronics Engineering, ComputerEngineering, or any related discipline. Good level of understanding and hands-on experience in Very Large Scale Integration (VLSI)design and physical design implementation. Prior experience in timing closure, clock/power distribution and analysis, RC extraction, andcorrelation. Hands-on experience in full-chip/sub-chip Static Timing Analysis, timing constraints generationand management, and timing convergence. Expertise in physical design and optimization: floorplan, placement, routing, cell sizing, buffering,logic restructuring to improve timing and power. Expertise in analyzing and converging crosstalk delay, noise glitch, and electrical/manufacturingrules in deep-sub-micron processes Understanding of process variation effect modeling and experience in design convergence takinginto account variations. Experience in critical path planning and crafting.1
Keyskills :
crosstalk delay Vlsi Timing Closure manufacturing rules critical path planning noise glitch rc extraction Static Timing Analysis
Infinecs
Job Source: www.infinecs.com
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