Job Location | Bayan, Malaysia |
Education | Not Mentioned |
Salary | Not Mentioned |
Industry | Other |
Functional Area | Not Mentioned |
Analog IC Layout Design EngineerResponsibilities include (but are not limited to): Work and lead junior engineer towards projects delivery with other layout and circuit designengineers to resolve any technical issues that will affect layout to ensure high quality. Utilize EDA tools (Cadence and Synopsys) for layout design and all related verification items,perform all layout activities as cell and block level creation, edit and full verification. Use state-of-the-art layout techniques for matching, ESD, latch-up prevention and parasiticreduction and work with an awareness and understanding of the process from physical point of view. Attending all relevant project meetings, continuous assessment and reporting of timescale risks. Where possible, use schematic driven layout and consider top level auto routing. Involve in review session and prepare all related document and data preparation for wafer tape out.Requirements Bachelors Degree Engineering in Electrical/Electronic, Physics, Computer or related fields. Must have Good verbal and written communication skills in English. Japanese is a plus Thorough understanding of integrated analog circuit design Thorough understanding of chip layout in cell and block level creation, edit and full verification. Experience with layout techniques for matching, ESD, latch-up prevention and parasitic reductionand work with an awareness and understanding of the process from physical point of view. Experience in analog IC/ mixed signals IC layout designs and verifications. Able to perform withideas on chip size reduction. Highly self-motivated and adaptable. Having the basic knowledge of CMOS related devises including high voltage and the skill ofdeciphering Design Manual.
Keyskills :
CMOS chip layout parasitic reduction latch-up prevention EDA Tools Esd Design Manual Cadence Synopsys Analog Circuit Design
Infinecs
Job Source: www.infinecs.com
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