SoC Synthesis Engineer

5.00 to 7.00 Years Penang, Bayan, Malaysia 10 Sep, 2023

Job Location	Penang, Bayan, Malaysia
Education	Not Mentioned
Salary	Not Mentioned
Industry	Semiconductor Manufacturing
Functional Area	Not Mentioned

We are hiring Senior / Staff / Senior Staff SoC Synthesis Engineer Key responsibilities:

Logic synthesis execution for optimal PPA using physically aware techniques with industry tools such as Design Compiler or Genus.
Responsible and drive SOC synthesis activities, Logical Equivalence and logic ECO
Formulate and improve on existing synthesis methodology
Synthesis using Low power design methodology with UPF, and power intent verification using design tools such as VCLP, CLP etc.
Work closely with FE engineers and Physical Design team on timing constraints for SOC partitions, PPA improvement, and synthesis flow enhancement
Explore and seek improvement on existing synthesis methodology

Requirements:

5years experience in synthesis and ASIC design flow
This position requires relevant technical knowledge of synthesis, static timing analysis, scripting, and logical equivalence check.
Familiar with UPF usage in synthesis for power domains and voltage area.
Hands-on experience in timing/SDC constraints development and management
Knowledge of timing PVT corners, variations, placement and routing to correlate results between synthesis and physical design
Proficient in scripting languages (Tcl and Perl). Experience with script-based tool automation and familiarity with EDA tools such as Design Compiler, Genus, PrimeTime etc. is a plus.
Competent in the closure of logic equivalence with functional ECOs in the mix. Familiar with relevant tools such as Formality and Conformal etc.
Familiarity with DFT and backend related methodology and tools.
Fluent and understanding of RTL Verilog/VHDL and be able to communicate efficiently with FE engineers to improve on synthesis quality
Knowledge of memory compiler would be added advantage

Keyskills :
Clp Perl Tcl Design Compiler Memory Compiler ASIC VHDL

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