SoC RTL Design Engineer

5.00 to 12.00 Years Penang, Bayan, Malaysia 10 Sep, 2023

Job Location	Penang, Bayan, Malaysia
Education	Not Mentioned
Salary	Not Mentioned
Industry	Semiconductor Manufacturing
Functional Area	Not Mentioned

We are hiring Senior Staff / Staff / Senior / Junior SoC RTL Design Engineer (Multiple positions available)Job Highlights

Responsible for RISC-V based SoC RTL design integration.
Perform SoC and IP subsystem RTL design integration which includes integration of key SoC IP subsystems & peripherals block .
Develop SoC integration and technical reference manual documentation.
Perform IP logic design on SoC required adaptation logic blocks.
Collaborate with Verification & FPGA engineers on functional/performance/integration simulation validation, FPGA prototyping and debug.
Perform front end quality checks ranging from RTL static & synthesizability checks, timing convergence, netlist quality checks and etc.
Optimize & maintain SoC RTL integration flow & scripts.
Work with Software Development Team on firmware driver and software requirements.

Requirements:

Bachelor / Master degree in Electrical & Electronic Engineering, Computer Engineering or equivalent.
Experience in SoC and/or IP logic design implementation and/or verification .
Experience with Verilog and System Verilog RTL.
Familiar with EDA tools such as Xcelium/Modelsim/VCS, Spyglass, industry leading logic synthesis and logic equivalency checks tools.
Knowledge in RISC-V / ARM architecture, AMBA/AXI protocol, interconnects and various IP Protocol.
FPGA prototyping and scripting skills in Perl, tcl, Python & shell is an added advantage.
Strong problem solver, good communication skills and team player.
12 years of relevant experience on SoC RTL integration or IP logic design for Senior Staff position, 8 years for Staff position, 5 years of relevant experience for Senior position.

Keyskills :
Eda Vcs Soc Perl Verilog Arm System Verilog Python Tcl RTL spyglass AMBA Axi Modelsim

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