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Senior Design Verification Engineer

4.00 to 6.00 Years   Penang, Bayan, Malaysia   02 Feb, 2024
Oppstar Berhad
Job LocationPenang, Bayan, Malaysia
EducationNot Mentioned
SalaryNot Mentioned
IndustrySemiconductor Manufacturing
Functional AreaNot Mentioned

Job Description

Responsibilities:

  • Perform pre-Si verification on various IP blocks and full-chip of FPGA/ASIC designs.
  • The job scope includes test plan definition, System Verilog/UVM test bench and content development, debugging and running regression to deliver good-quality design.
  • Candidate will work closely with team and interact with product/IP architect, logic design engineer, DFX owner, and design automation engineer to ensure high quality design validation.
Qualifications:
  • BSEE/MSEE/PhD with at least 4 years relevant experience
  • Experience in functional verification that may include test planning, test bench development, stimulus generation, reference model and assertion checkers development and functional coverage.
  • Experience with modern verification techniques e.g. System Verilog OVM/UVM, assertion-based verification, constrained random verification methodologies.
  • Familiar with IP protocols (e.g. HSST, Ethernet, PCIe, DDR), FPGA and/or ARM architectures.
  • Hands-on experience in various logic designs and verification tools and flow e.g. from Cadence, Mentor Graphics and/or Synopsys.

Keyskills :
DDR Fpga Pcie Ethernet System Verilog ASIC Mentor Graphics Cadence Uvm Synopsys

About Company

Destination Hotels is a privately held lodging management company headquartered in Englewood, Colorado. It is the United States' largest independent hospitality management company, representing 40 luxury and upscale hotels, resorts and golf clubs internationally

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