Design Verification Engineer

0.00 to 2.00 Years Penang, Bayan, Malaysia 10 Sep, 2023

We are hiring Staff / Senior / Junior Verification Engineer for IP (Multiple positions available)

Responsible for IP level and/or SOC level verification.
Develop verification plan for complex digital IP from design spec, work closely with design engineers to identify important verification scenarios.
Create verification environment/testbench with Bus Functional Model (BFM) using SystemVerilog, UVM and/or System C.
Identify and implement functional coverage and SystemVerilog Assertions to catch functional bugs and to boost design quality prior to tape-out.
Develop directed/use case/random test cases using SystemVerilog, analyse test results, debug tests and improve verification quality.
Knowing to use Formal verification with SystemVerilog Assertion (SVA) to verify IP block is a plus.

Requirements:

Bachelor/Master Degree in Electrical & Electronics/Computer Engineering or equivalent.
Familiar with AMBA bus protocol (AXI, CHI, ACE, APB).
Experience with verification methodology such as SystemVerilog, OVM, UVM, SystemC.
Experience with functional coverage/SVA assertions and test sequence/case writing.
Experience with the full verification execution cycle.
Experience in developing measurable verification plan.
Experience with function verification for common SoC building blocks and verification IP for NOC/Interconnect/Fabric/PCIE, etc. are added advantages.
Strong problem solver, communicator and team player.
Scripting skills in Perl, Python, TCL, shell, etc.

Keyskills :
Perl Python Tcl System C Uvm systemverilog

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