| Job Location | Dubai, UAE |
| Education | Not Mentioned |
| Salary | Not Mentioned |
| Industry | Not Mentioned |
| Functional Area | Not Mentioned |
F.A.S.T. is developing what would be the world's first all-digital S-Band radar chipset ? a homegrown UAE ITAR-free capability. The RFIC Engineer will own the chip-level design, from schematic to GDSII, and drive the programme through tape-out.Key Responsibilities? Design RF/mixed-signal ICs for S-Band radar transceivers in 180 nm / 130 nm RFCMOS or BiCMOS processes? Own circuit blocks: LNA, PA, mixer, PLL/VCO, ADC/DAC interface circuits? Lead schematic capture, layout, and post-layout simulation in Cadence or equivalent EDA tools? Manage tape-out submissions, MPW shuttle selection, and wafer testing? Co-author patent applications for novel circuit topologies? Work with the RF systems team to meet S-Band radar transceiver specifications?Required Qualifications? MSc or PhD in Microelectronics, Electrical Engineering, or VLSI Design? 3+ years RFIC or mixed-signal IC design experience? Hands-on Cadence Virtuoso or equivalent; experience with TSMC or similar CMOS processes? Understanding of S-parameter characterisation, noise figure, linearity metrics (IIP3, P1dB)SkillsBonus / Differentiators? Prior microwave IC (MMIC) design at 2?4 GHz bands? Experience with radar-on-chip architectures or phased-array IC design? Publication record or co-patents in RF circuit design.
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