| Job Location | Hyderabad, Pakistan |
| Education | Not Mentioned |
| Salary | Not Mentioned |
| Industry | Other Business Support Services |
| Functional Area | Not Mentioned |
Cyient is a global engineering and technology solutions company.ÿAs a Design, Build, and Maintain partner for leading organizations worldwide, we take solution ownership across the value chain to help clients focus on their core, innovate, and stay ahead of the curve. We leverage digital technologies, advanced analytics capabilities, and our domain knowledge and technical expertise, to solve complex business problems.With over 15,000 employees globally, we partner with clients to operate as part of their extended team in ways that best suit their organization?s culture and requirements. Our industry focus includes aerospace and defence, healthcare, telecommunications, rail transportation, semiconductor, geospatial, industrial, and energy.Create testbench specifications and coverage plans Implement constrained-random sequences, agents, and environments using the UVM methodology.Developing and maintaining complex verification environments using methodologies (UVM, SV)Writing test plans, creating test benches to execute those test plans, analyzing coverage and identifying and fixing test bench holes, running regressions and filing bug reportsExcellent debugging skillsgood communication skillsSkills & ExperienceCommunication, Design Verification, Power Management, Test Bench, Test Planning, USB (Inactive), USB 2.0 (Inactive), Verilog, Writing Test PlansCyient is an Equal Opportunity Employer.Cyient recruits, employs, trains, compensates, and promotes regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender, gender identity or expression, veteran status, and other protected status as required by applicable law. We are proud to be a diverse and inclusive company where our people can focus their whole self on solving problems that matter.
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